For modern processors there is a difference between logical registers and physical registers that actually store the data. Logical registers are labels defined by the instruction set architecture. These labels do not address specific hardware within a processor. Indeed, a logical register label may refer to a first register for a first instruction in a program and may refer to an entirely different register for another instruction. Physical registers are storage units within a processor core. Logical registers are mapped to physical registers. The mapping changes over time. Typically, the identity and use of physical registers cannot be determined by a processor's instruction set architecture.
For example, the instruction “MOV EAX, 0” (Store the value 0 in register EAX) does not refer to a physical register location in a processor. Instead, it refers to a “logical register,” a fictional register that may be mapped to various physical registers within a processor as the processor advances through executable program instructions. This property of modern processors is a well-known byproduct of out-of-order processing.
The inventors of the present invention noted that the values stored in physical registers often exhibit a high degree of redundancy. For example, consider an example where three variables are initialized to zero in a processor core. In traditional processors, the three variables each would occupy different physical registers. This is inefficient because, so long as the values are the same, the contents of the three variables could be stored in a single physical register. The other two registers could be used for other purposes. U.S. patent application Ser. No. 08/348,403, entitled “Unified Renaming Scheme,” filed Jul. 7, 1999, discloses a register renaming scheme that maps multiple logical registers to a single physical register.
A virtual naming scheme (sometimes referred to as “late binding”) has recently been proposed for physical registers. See, Gonzalez, et al., “Virtual Physical Registers,” Proc. 4th Int'l Symp. High Perf. Computer Architecture (February 1998). Under the virtual renaming scheme, physical registers are allocated for data generated during instruction execution after the data is generated. In traditional processors, physical locations had been allocated to instructions much earlier, when the instructions were loaded in the processor core. Because the virtual renaming techniques shorten the amount of time that a physical register is allocated to a particular instruction, Gonzalez's techniques permit a fixed number of physical registers to support a greater number of instructions than could have been supported when registers were allocated upon receipt of an instruction.
Accordingly, there is a need in the art for a virtual register renaming scheme that permits multiple logical registers that have the same value to map to a single physical register wherein that value is stored.